cadence design sys inc (CDNS) Key Developments
HiSilicon Technologies Expands Adoption of Cadence Design Systems, Inc. Tools and IP for Advanced-Node FinFET Designs
Dec 1 14
Cadence Design Systems Inc. announced that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16 nanometer FinFET designs, and to collaborate on the design flow for 10 nanometer and 7 nanometer nodes. HiSilicon has also broadly adopted Cadence digital and custom/analog verification solutions, and has licensed Cadence DDR IP and the Cadence 3D-IC solution to deploy multiple heterogeneous dies in a single package on a silicon interposer substrate. For the digital flow, the agreement includes access to Cadence Encounter Digital Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, and Quantus QRC Extraction Solution. For custom/analog design, HiSilicon designers are using Cadence Virtuoso custom design platform, Spectre simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor. The agreement also includes an increase in licenses of Incisive Enterprise Simulator for advanced verification. For 3D-IC designs, HiSilicon is utilizing the Cadence 3D-IC solution, which includes Encounter Digital Implementation System and Allegro tools for IC/package co-design, and Voltus and Sigrity solutions for power, thermal and signal integrity verification.
Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development
Nov 10 14
Cadence Design Systems Inc. announced that Sonics Inc. has adopted Cadence(R) JasperGold(R) Apps in the formal verification methodology for its intellectual property (IP). Sonics' on-chip network IP integrates multiple heterogeneous cores in a system-on-chip (SoC) using configurable interconnect fabric and multiple, on-chip communication protocols including the native PIF interface of Cadence(R) Tensilica(R) Xtensa(R) DPUs. Sonics is initially deploying the JasperGold Apps to speed the extensive validation of its protocol conversion logic. Part of the Cadence System Development Suite, JasperGold Apps perform multiple formal-based verification tasks and leverage a common formal verification platform, database and user interface. JasperGold Apps automate property creation for many common verification tasks, enabling rapid adoption by both design and verification engineers without previous formal experience. All JasperGold Apps leverage the Cadence Jasper Visualize(TM) graphical visualization and debug technology for fast debugging and a consistent user experience. Verification of configurable interfaces is a challenging task, as traditional simulation environments aren't well suited to handle their complexity. Exhaustive verification of highly configurable on-chip networks that integrate multicore SoCs requires both stimulus-driven simulation and formal proof technologies. To ensure the quality IP, the network transactions must be checked across communication protocol boundaries. Simulation alone is insufficient to fully check the transfer function of the network. JasperGold readily accepts commonly available formats like SystemVerilog Assertions (SVA) as its input and has easily scripted setup controls, enabling easy integration with other verification environments. By allowing Sonics to use exactly the same SVA protocol checkers for both simulation and formal verification, the use of JasperGold Apps can help eliminate an entire class of bring-up and ongoing issues.
Cadence Design Systems Inc. Announces First 25G Ethernet Verification IP
Oct 27 14
Cadence Design Systems Inc. announced the Verification IP (VIP) supporting the new 25-Gigabit (25G) Ethernet specification. The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence(R) 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected. This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25% bandwidth improvement compared to 40G.
Cadence Design Systems Inc. Announces Virtuoso Liberate AMS Characterization Solution
Oct 27 14
Cadence Design Systems Inc. announced the Cadence(R) Virtuoso(R) Liberate(TM) AMS characterization solution, first dynamic simulation characterization solution for mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os. Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff. With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty(TM) representations are required for all blocks in the design including mixed-signal macros. To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library. To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre(R) XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks. This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models. For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.
Cadence Design Systems Inc. Announces Broad Portfolio of 3D Memory Verification IP
Oct 23 14
Cadence Design Systems Inc. announced the immediate availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications. Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager. Additionally, the models support all third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.