integrated device tech inc (IDTI) Key Developments
Integrated Device Technology, Inc. Launches RapidIO 40-100 Gbps Interface Portfolio, Reducing Latency and Boosting Bandwidth for Communications and Computing
Dec 9 14
Integrated Device Technology, Inc. announced the launch of a RapidIO® 40-100 Gbps interface product portfolio, developed to lower latency while improving bandwidth for high-performance computing (HPC), wireless, analytics and embedded applications. For the first in a series of products planned, IDT is introducing a 40 Gbps RapidIO 10xN IP core for ASIC, CPU, processor, DSP, GPU and FPGA partners and end customers, supporting silicon solutions with process technology nodes from 45 down to 16 nanometers. The RapidIO 40 Gbps IP core is designed to serve as a basic building block and gateway between processing elements to create low-latency, scalable, energy-efficient computing. The lower latency and higher speed interface products will be essential for the efficient and cost-effective management and analysis of the massive volumes of data generated by electronics. The new RapidIO 40 Gbps 10xN IP core will be used in upcoming RapidIO 40-100 Gbps switching, bridging, processor and memory controller products, including the switching collaboration between IDT and eSilicon to develop 100 ns latency RapidIO switches operating at 40 Gbps per port. The solutions will be backward compatible with the millions of RapidIO products on the market operating at 10-20 Gbps data rates.
Integrated Device Technology, Inc. Presents at Barclays Capital Global Technology Conference, Dec-09-2014 04:00 PM
Nov 21 14
Integrated Device Technology, Inc. Presents at Barclays Capital Global Technology Conference, Dec-09-2014 04:00 PM. Venue: Palace Hotel, 2 New Montgomery Street, San Francisco, California, United States. Speakers: Brian C. White, Chief Financial Officer and Vice President.
Integrated Device Technology, Inc. Introduces New Family of Magnetic Induction Wireless Power Transmitters
Nov 20 14
Integrated Device Technology, Inc. introduced a new family of magnetic induction wireless power transmitters designed for the next generation of wireless charging products, delivering greater flexibility and ease of use while reducing overall development cost through a high level of integration. As an expansion to an existing broad portfolio of products, the ultra-compact transmitters feature low electromagnetic interference (EMI) and high efficiency, making them ideal for a wide variety of applications, including wearables, smart phones and furniture. The P9235 and P9236 transmitters are compliant with the latest Wireless Power Consortium (WPC) Qi standard, while the P9234 is a Power Matters Alliance (PMA)-compliant device. IDT is also introducing a proprietary-mode device, the P9231, which operates at up to 1MHz of resonance frequency, allowing for a smaller coil. To complete the product offering, IDT's P9230 is a dual-mode transmitter, supporting both WPC and PMA standards. Collectively, the P923x family addresses all of the various WPC low-power coil configurations. Featuring an integrated 32-bit ARM(R) Cortex(R)-M0 processor, the P923x family offers a high level of programmability and flexibility while consuming ultra-low standby power to meet Energy Star requirements. The transmitters span input voltages ranging from 4.0 V to 21 V and target applications requiring from 0.5 to 10W of power. In addition, the devices offer a high level of integration, including all digital and analog functions, which minimizes the number of external components while reducing overall system cost.
Integrated Device Technology, Inc. Introduces New High-Performance Synthesizer
Nov 20 14
Integrated Device Technology, Inc. introduced a new high-performance synthesizer with ultra-low phase jitter for reducing bit error rates in today's serial data communications systems. The 8T49NS010 synthesizer with an integrated fanout buffer/divider delivers high-performance clocks for demanding applications, and is ideal for 40GE and 100GE telecommunications and networking systems. The 10-output synthesizer provides a high-frequency clock with 86 fs RMS phase jitter over the standard 12 kHz to 20 MHz integration range. The 8T49NS010 features an integrated fanout buffer, removing the issues of additive phase jitter and noise coupling from oscillator to fanout buffer. The chip supports programmable configurations and output levels to satisfy the requirements of a variety of applications. The 8T49NS010 is configurable through an I(2) C serial interface and operates over an industrial temperature range. In addition to output power-down, it supports two logic levels for its differential outputs; the first provides an LVPECL output level with 750mV typical swing, while the second provides a similar swing and output level with no external DC termination. The device uses an external fundamental mode crystal, alleviating the expense and availability issues associated with high-end oscillators. Detailed specs include typical phase noise jitter of only 86fs from 12kHz to 20MHz; an LVPECL output level with 750mV typical swing requiring no DC termination; and noise floor of -161 dBc/Hz.
Integrated Device Technology, Inc. Accelerates Computing Breakthrough with RapidIO-Based Clusters Ideal for Gaming, Analytics
Nov 18 14
Integrated Device Technology, Inc. announced the development of a groundbreaking compute architecture designed to handle the immense data demands of online gaming, high-performance computing and analytics through high-density, low-latency clusters of connected mobile processors. In conjunction with Orange Silicon Valley, the semiconductor company co-developed a massive highly scalable, low-latency cluster of low-power NVIDIA(R) Tegra(R) K1 mobile processors, using IDT's RapidIO(R) interconnect technology to connect multiple nodes at up to 16 Gbps. The architecture can scale to more than 2,000 nodes in a rack and enables ultra-high Gflop density and energy efficiency not achievable with PCI Express(R) or Ethernet technologies. By integrating a large volume of low-power GPUs in a server rack at scale, this industry first creates a clear path to massive cloud-based clusters for analytics and gaming. This architecture delivers--in an energy- and latency-efficient manner--remarkable computing horsepower in addressing the challenge of co-locating analytics in the approximately 2 million base stations deployed annually in wireless networks. The architecture allows for 60 nodes on a 19-inch 1U board, with more than 2,000 nodes in a rack. Any node can communicate with another node with only 400 ns of fabric latency. Memory-to-memory latency is less than two microseconds. Each node consists of a Tsi721 PCIe(R) to RapidIO NIC and a Tegra K1 Mobile Processor with 384 Gflops per 16 Gbps of data rate, or 24 floating point operations per bit of I/O. This will be valuable at the rack level in data centers and at the individual analytics server level for wireless access networks.