xilinx inc (XLNX) Key Developments
Xilinx Inc. Announces 4.4M Logic Cells
Dec 10 13
Xilinx Inc. announced a 4.4M logic cell device, and delivering an extra node worth of customer value and announced, the Virtex(R) UltraScale(TM) VU440 3D IC extends Xilinx's from 2x at 28nm to 4x at 20nm. Using advanced 3D IC technology, the VU440 device delivers more at 20nm than publicly stated competitive plans at 14/16nm. The Virtex UltraScale VU440 device, delivering 50M equivalent ASIC gates for next generation production and prototyping applications. 20nm Virtex UltraScale devices also provide the highest system performance and bandwidth for single chip implementations of 400G MuxSAR, 400G Transponder and 400G MAC-to Interlaken bridge applications. The Virtex UltraScale family gives customers new levels of performance, systems integration, and bandwidth with the added benefits of re-programmability. The scalability of the Virtex UltraScale VU440 device is made possible by its ASIC-class architecture for up to 90% utilization featuring next generation routing, ASIC-like clocking, power management, elimination of interconnect bottlenecks, and critical path optimizations. Along with major advancements to key architectural blocks--such as wider multipliers, high speed memory cascading, 33G capable transceivers, and the addition of integrated 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP cores, these devices enable multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates. Key to the device's bandwidth and capacity is second generation Stacked Silicon Interconnect (SSI) technology. Built on TSMC's CoWoS manufacturing technology, this generation of SSI technology features 5x more inter-die bandwidth and a unified clocking architecture across slice boundaries to deliver a virtual monolithic design experience. Xilinx's SSI technology enables Xilinx to deliver devices with 2-4x the capacity of competing devices and continue to stay ahead of what Moore's Law could otherwise offer. Xilinx UltraScale devices deliver an ASIC-class advantage with the industry's only ASIC-class programmable architecture that scales from 20nm planar through 16nm FinFET technologies and from monolithic through 3D ICs. Through a combination of TSMC's edge technology and co-optimization with the Vivado ASIC-strength Design Suite, and recently introduced UltraFast(TM) design methodology, Xilinx is one to two years ahead in delivering another 1.5x to 2x realizable system-level performance and integration. Xilinx(R) UltraScale(TM) devices are supported in the Vivado(R) Design Suite 2013.
Xilinx, Inc. Announces 20nm All Programmable Ultrascale Portfolio Available with ASIC-Class Architecture and ASIC-Strength Design Solution
Dec 10 13
Xilinx Inc. announced availability of its 20nm All Programmable UltraScale(TM) portfolio with product documentation and Vivado(R) Design Suite support. These devices deliver an ASIC-class advantage with the ASIC-class programmable architecture coupled with the Vivado ASIC-strength design suite and UltraFast(TM) design methodology. The new Xilinx(R) UltraScale product portfolio extends Xilinx's Kintex(R) and Virtex(R) FPGA and 3D IC families, based on the UltraScale architecture and the superior gate density of TSMC's 20SoC process. UltraScale devices enable 1.5x to 2x realizable system performance and integration, and consume up to half the power, relative to currently available solutions. These devices deliver next generation routing, ASIC-like clocking, and enhancements to logic and fabric to eliminate interconnect bottlenecks while supporting consistent device utilization of more than 90% without performance degradation. The new Kintex(R) UltraScale(TM) FPGAs deliver up to 1.16M logic cells, 5,520 optimized DSP slices, 76 Mbits of BRAM, 16.3Gbps backplane-capable transceivers, PCIe(R) Gen3 hard blocks, integrated 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP Cores, and DDR4 memory interfaces. Initially introduced as part of the 28nm Xilinx 7 series family, Kintex devices established the new mid-range category of best price-performance at the lowest power. Kintex UltraScale devices are designed to continue leadership in this category to meet the requirements for the growing number of key applications including 8K/4K Super High Vision Displays and Equipment, 256-channel Ultrasound, 8X8 Mixed Mode LTE and WCDMA radio with smart beamforming, 100G Traffic Management/NIC, DOCSIS 3.1 CMTS equipment. The new Virtex(R) UltraScale(TM) devices provide unprecedented levels of performance, system integration and bandwidth on a single chip. The large family member delivers 4.4M logic cells, 1,456 user I/Os, 48 x 16.3 Gb/s backplane-capable transceivers and 89 Mbits of Block RAM, breaking previous records by more than doubling Xilinx's industry's high capacity Virtex-7 2000T device and delivering a staggering 50M equivalent ASIC gates. Virtex UltraScale devices include 28Gb/s backplane-capable and 33Gb/s chip-to-optics transceivers, in addition to integrated PCIe Gen3, 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP cores, and DDR4 memory interfaces to support multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates. The system performance and capacity delivered with the Virtex UltraScale family makes these devices the logical choice for the most challenging applications such as single chip 400G MuxSAR, 400G Transponder, 400G MAC-to-Interlaken bridge, emulation and Prototyping.
Xilinx, Inc. Announces Comprehensive Functional Safety Design Package Enables Smarter Factories and Medical Equipment
Nov 26 13
Xilinx Inc. announced that its comprehensive functional safety design package for industrial, automotive, medical, aerospace and defense applications according to IEC 61508 and ISO 26262 safety standards. Xilinx's functional safety package includes a TUV SUD certified design methodology and tools that increase design productivity and reduce certification risks. Xilinx's certified functional safety design methodologies allow system designers to deliver highly differentiated, highly integrated safety compliant solutions with the fastest time to market. The Isolation Design Flow (IDF) and Isolation Verification Tools (IVT) provide a unique and automated methodology to separate system- critical and non-system-critical functions within the same FPGA through physical area isolation. The independent designs, in isolated locations, can be changed at any time without impacting other isolated locations, which reduces design complexity and development time.
Xilinx Inc. Presents at BMO Capital Markets 2013 Technology & Digital Media Conference, Dec-10-2013 09:30 AM
Nov 26 13
Xilinx Inc. Presents at BMO Capital Markets 2013 Technology & Digital Media Conference, Dec-10-2013 09:30 AM. Venue: Grand Hyatt New York, 109 East 42nd Street at Grand Central Terminal, New York, NY 10017, United States. Speakers: Moshe N. Gavrielov, Chief Executive Officer, President and Director.
Xilinx Inc. Announces Accelerated Design Productivity for Machine Vision Applications, Leveraging HALCON and VisualApplets Development Platforms
Nov 25 13
Xilinx Inc. announced accelerated design productivity for machine vision applications, leveraging HALCON and VisualApplets development platforms to create an end-to-end Smarter Vision development environment for the Zynq(R)-7000 All Programmable SoC. HALCON software from MVTec for machine vision provides high-performance and comprehensive support for video analytics and runs on multicore platforms like the Zynq All Programmable SoC. HALCON includes a library of more than 1800 operators for blob analysis, morphology, matching, measuring, identification, and 3D vision. VisualApplets from Silicon Software provides advanced image processing libraries and high-level design entry and simulation tools that enable users to quickly and efficiently program FPGA hardware for industrial image processing. The strong collaboration of Xilinx with HALCON and VisualApplets creates an end-to-end Smarter Vision development environment for Zynq-7000 All Programmable SoC users that reduces design cycles and time to market. Offering both hardware and software re-programmability, the Zynq-7000 SoC is well suited for the system flexibility and customization required by machine vision applications. The dual-core ARM(R) Cortex(TM)-A9 MPCore(TM) processing system inherent in the Zynq-7000 architecture provides a software programming platform that runs application software and executes networking and management tasks, while the Xilinx(R) 28nm programmable logic provides a hardware programming platform capable of real-time performance for image processing, filtering and scaling. Placing key image processing functions inside the FPGA fabric accelerates performance faster than a traditional software approach.