Semiconductors and Semiconductor Equipment
Company Overview of Tabula, Inc.
Tabula, Inc., a fabless semiconductor company, develops 3D programmable logic devices (PLD). It provides ABAX 3PLD Devices, a category of general-purpose chips; I-100, a device that provides a bridge between 100Gbps Ethernet and Interlaken the ascending interconnect standard for communications; Ternary Search Engines that enable smooth transition from IPv4 to IPv6 while giving the opportunity to differentiate the platform; I-40, a device that offers a bridge between 40Gbps Ethernet and Interlaken the ascending interconnect standard for communications; and NetASAPdc, a virtualization optimized 4x10 GbE router/switch/firewall/programmable NIC for data centers, hosted ISP services, and other ap...
3250 Olcott Street
Santa Clara, CA 95054
Founded in 2003
Key Executives for Tabula, Inc.
Chief Executive Officer and Director
Vice President of Human Resources
Vice President of Hardware Development
Compensation as of Fiscal Year 2013.
Tabula, Inc. Key Developments
MoSys Announces Tabula Support of GigaChip Interface
Nov 21 13
MoSys announced that Tabula, Inc., advancing high-performance programmable logic solutions for network infrastructure systems, supports the GigaChip(TM) Interface. As networking equipment transitions from 10G to 40G to 100G and beyond, greater access to memory is increasingly required to execute complex packet header processing operations for line rate switching, routing, monitoring and security. Programmable logic devices from Tabula offer substantial on-chip bandwidth and off-chip memory capacity using commodity external memory. However, traditional memory solutions lack sufficient access to memory, exposing a bottleneck which strangles the overall system performance. Using MoSys(R) Bandwidth Engine(R) serial memory solutions combined with the highly efficient GigaChip Interface alleviates this chokepoint in the system by providing four times the access performance of traditional memory solutions.
Tabula Announces the Availability of Stylus Compiler Version 2.7.2
Sep 4 13
Tabula, Inc. announced the availability of version 2.7.2 of its Stylus(R) compiler supporting its ABAX(R)(2) P-Series of devices. The new capabilities of Stylus compiler include a 100G top-of-rack (ToR) switch reference design targeting next-generation datacenters, along with several new features aimed at further improving user experience. This reference design lays the foundation for an Ethernet switch development platform using ABAX(2) devices. With the advance of 100 Gigabit Ethernet (GbE) technology for datacenters, there is a growing demand for silicon systems that support line-rate packet processing. This reference design demonstrates how the Spacetime(R) architecture combined with the ABAX(2) device's rich feature set and capabilities can be applied to these high-performance systems in the domain of 100 GbE packet processing and switching. This reference design consists of a collection of functional blocks which provides a platform for classification, filtering, forwarding and scheduling of packets on networks with 100 GbE interfaces. Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula's 3D Spacetime architecture, unleashing the ABAX(2) 3PLDs' unmatched capabilities and achieving unparalleled performance with surprising ease. The software integrates cutting-edge timing-closure technologies, including sequential timing, router-aware placement, and automatic co-optimization of performance and density. In addition, to help users take full advantage of the ABAX(2) P-Series of device's unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-port memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device's on-chip RAM blocks.
Tabula, Inc. Announces Availability of Stylus Compiler Version 2.7.1
Aug 1 13
In a continuing move to help make network infrastructure systems more responsive to applications' dynamic needs, Tabula, Inc. announced the availability of version 2.7.1 of its Stylus(R) compiler supporting its ABAX(R) P-Series of 3D programmable logic devices (3PLDs). Stylus 2.7.1 further eases design of complex high-bandwidth systems with the addition of support for the hardware description and verification language SystemVerilog. To help accelerate the development of high-performance applications, the software also features new design examples showing how to utilize Spacetime(R) technology with its many-ported memory blocks and how to build high-performance, small-footprint finite state machines (FSM) using ROM structures. This release also includes a 1 giga-samples per second Fast Fourier Transform (FFT) IP core demonstrating the digital signal processing potential of the ABAX family of devices. The new capabilities and design kits introduced in the Stylus 2.7.1 release include: SystemVerilog support: Addressing the increasing customer demand for a combined design and verification language, Tabula's Stylus compiler can now process code written following SystemVerilog syntax. This capability not only increases the supported application domains, but also prepares the path for the future use of assertion-based design debug; Soft IP cores: A high-performance 1 Gsps FFT IP core is now available on the Tabula IP Management System; This core can be configured for transforms of 1K, 2K, 4K, 8K, 16K or 64K points; Design examples: A 12-ported RAM block design example showing how to express many-ported memory blocks and manage port access ordering in a Spacetime-based fabric; A ROM-based finite state machine design example to illustrate how Spacetime enables new approaches to sequential logic design ideally suited to high-performance datapath systems.
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