September 01, 2014 2:41 PM ET

Semiconductors and Semiconductor Equipment

Company Overview of Tabula, Inc.

Company Overview

Tabula, Inc. provides programmable logic solutions. The company offers 3D programmable logic devices for packet processing applications, and enable users to process multiple 100 Gbps packet streams on a single device; 3D tri-gate transistors; Spacetime, a technology that enables a new category of programmable logic devices that reconfigure on the fly at multi-GHz rates executing each portion of a design in an automatically defined sequence of steps; a development board to enable users to evaluate and design with packet processing pre-engineered solutions; NetABAX2 PCIe card for Ethernet and software defined networks to provide support for high-speed packet parsing, switching, routing, monito...

3250 Olcott Street

Suite 1120

Santa Clara, CA 95054

United States

Founded in 2003

Phone:

408-986-9140

Fax:

408-986-9146

Key Executives for Tabula, Inc.

Chief Executive Officer and Director
Age: 61
Corporate Controller
Chief Marketing Officer and Senior Vice President
Senior Vice President of Product Development
Compensation as of Fiscal Year 2014.

Tabula, Inc. Key Developments

Tabula, Inc. Announces Availability of Stylus Compiler Version 2.8.2

Tabula, Inc. announced the availability of version 2.8.2 of its Stylus compiler, supporting its ABAX (2) P-Series of devices. Stylus 2.8.2 includes a new 3 x 40G-to-100G low-latency Ethernet bridge reference design, as well as a high-performance search engine soft IP core developed in collaboration with Algo-Logic Systems. These and the many other capabilities included in this release are designed to facilitate next-generation 100G networking equipment development and to further improve user experience. The new capabilities and design kits introduced in the Stylus 2.8.2 release include: A 3 x 40G-to-100G Ethernet bridge: this reference design implements a fully functional 40G Ethernet to 100G Ethernet bridge providing transparent bidirectional bridging between the 40 GigE ports and the 100 GigE port and utilizing deficit-weighted round-robin (DWRR) traffic scheduler for aggregation of the 40 GigE ports. Features include: Three 40G Ethernet ports, One 100G Ethernet port, Forwarding table using Algo-Logic System's EMSE2 soft IP core for 100 GigE traffic, Support of multicast, broadcast and jumbo packets, Host management interface serial port; EMSE2 Hybrid soft IP core: created in collaboration with Algo-Logic Systems, this second generation exact-match search engine (EMSE2) delivers high-performance exact-match search capabilities. The EMSE2 Hybrid core performs up to 150 million searches per second (MSPS), sufficient for a 100G Ethernet traffic stream with minimum-sized 64-byte packets. If additional performance is needed, it is possible to use two or more replicated tables simultaneously. The core supports a wide range of key sizes, including up to 1.5 million entries, and very wide 640-bit keys for even the most demanding applications; DDR3 multi-port front-end reference (MPFE) design: the DDR3 MPFE allows up-to-eight independent (yet synchronous) hosts to drive a single DDR3 hard controller. The MPFE reference design has the following features: Enables up to eight independent ports (operating on the same clock) to drive a single hard DDR3 controller, Supports up to 2133 MT/s ×72 DDR3 throughput, Maintains a user interface that is consistent with the Tabula DDR3 subsystem, enabling easy integration into an existing design; Uses deficit round-robin arbitration to cycle between valid ports to optimize DDR3 efficiency.

Tabula, Inc. Announces Availability of Stylus Compiler Version 2.8.1

Tabula, Inc. announced the availability of version 2.8.1 of its Stylus(R) compiler, supporting its ABAX(R)2 P-Series of devices. Stylus 2.8.1 includes MoSys' GigaChip Interface (GCI) and Tamba Networks' soft IP cores, as well as a high-performance search engine reference design developed in collaboration with Algo-Logic Systems. These and the many other capabilities included in this release are designed to facilitate next-generation 100G networking equipment development and to further improve user experience. The new capabilities and design kits introduced in the Stylus 2.8.1 release include: MoSys' GCI soft IP core: Designed to interface with MoSys' Bandwidth Engine devices, the 90%-efficient GigaChip interface protocol enables high-bandwidth, high-efficiency chip-to-chip communications necessary for high-performance switching, routing, monitoring, and content processing functions. In addition, the core includes an automatic error recovery mechanism in the event of a channel CRC error to guarantee end-to-end data integrity and system reliability. Tamba Networks' universal Interlaken soft IP core: Tamba Networks offers the industry's lowest latency and smallest sized solution for the Interlaken communication protocol. The Interlaken IP core is also highly configurable to match system requirements including bandwidth of up to 600 Gbps and a lane count of up to 32. The initial configurations supported in this release are 12 × 10G and 8 × 7.5G Interlaken and Interlaken Look-Aside. The core is fully compliant to the Interlaken Protocol Definition revision 1.2. Titan IC regular expression processor (RxP) soft IP core: The RxP regular expression processor core is scalable for 10-40 Gb/s throughput. The core supports a large rule database of up to 10,000 rules using ABAX2P1 on-chip caches or 1M rules using optional, external DDR3 memory. It achieves this combination of high throughput and database depth by handling multiple characters and multiple regular expressions in parallel, including cross packet inspection. The core operates in an in-line or look-aside, accelerator role. NetASAP search reference design: Created in collaboration with Algo-Logic Systems, the NetASAP reference design provides L2/L3 routing capability for four 10 Gbps Ethernet ports. Routing logic is implemented using the Algo-Logic ATSE engine with 4K entries and 320-bit keys. This reference design supports two levels of priority queuing per Ethernet port with configurable queue depth of up to 1MB per port using on-chip memory only. Northwest Logic's configurable PCIe Gen 2 soft IP core; up to 15% runtime reduction. Added capabilities: In excess of 200 new features and improvements to usability, including enhanced timing debug capabilities, that contribute to Tabula's objective to make high-performance design easy.

MoSys Announces Tabula Support of GigaChip Interface

MoSys announced that Tabula, Inc., advancing high-performance programmable logic solutions for network infrastructure systems, supports the GigaChip(TM) Interface. As networking equipment transitions from 10G to 40G to 100G and beyond, greater access to memory is increasingly required to execute complex packet header processing operations for line rate switching, routing, monitoring and security. Programmable logic devices from Tabula offer substantial on-chip bandwidth and off-chip memory capacity using commodity external memory. However, traditional memory solutions lack sufficient access to memory, exposing a bottleneck which strangles the overall system performance. Using MoSys(R) Bandwidth Engine(R) serial memory solutions combined with the highly efficient GigaChip Interface alleviates this chokepoint in the system by providing four times the access performance of traditional memory solutions.

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