July 28, 2014 3:46 PM ET

Semiconductors and Semiconductor Equipment

Company Overview of Open-Silicon, Inc.

Company Overview

Open-Silicon, Inc. designs and manufactures semiconductors. The company focuses on SoC realization for traditional ASIC, develop-to-spec, and derivative integrated circuits. It offers SoC architecture, system design, physical design, IP, software, and semiconductor manufacturing services; and OpenMODEL, an ASIC development process. The company was founded in 2003 and is headquartered in Milpitas, California with additional offices in Eau Claire, Wisconsin; Raleigh, North Carolina; Milpitas, California; and Bengaluru and Pune, India.

490 North McCarthy Boulevard

Suite 220

Milpitas, CA 95035

United States

Founded in 2003

Phone:

408-240-5700

Fax:

408-240-5701

Key Executives for Open-Silicon, Inc.

Senior Vice President of Finance
Chief Operating Officer and Managing Director of India Operations
Vice President of Operations & Technology Development
General Manager
Compensation as of Fiscal Year 2014.

Open-Silicon, Inc. Key Developments

Xilinx, Inc. and Open-Silicon, Inc. Announces Hybrid Memory Cube Controller IP for Xilinx Virtex(R)-7 FPGAs

Xilinx, Inc. and Open-Silicon, Inc. announced Hybrid Memory Cube (HMC) controller IP for Xilinx Virtex(R)-7 FPGAs. The high-performance nature of Virtex-7 FPGAs enables system developers to take advantage of the ultra-high memory bandwidth of the Hybrid Memory Cube and utilize the host-side IP to decrease time to market while providing over 1 Tb/s of serial bandwidth. Hybrid Memory Cube is a high performance memory solution that delivers unprecedented levels of bandwidth, power efficiency and reliability for networking and computing systems. The availability of new host-side HMC Controller IP furthers the widespread adoption of this revolutionary technology. The Open-Silicon HMC Controller IP offers a seamless interface to HMC. The high-performance controller offers an ultra-low latency core coupled with a flexible user interface. Optimized for Xilinx Virtex-7 FPGA implementation, the IP supports HMC links operating at 12.5 Gb/s per lane. The HMC controller has been tested on Xilinx Virtex-7 FPGAs and, along with the accompanying software stack, allows for the quick integration and evaluation of the HMC technology and performance testing of the HMC links.

Open-Silicon, Inc. and GLOBALFOUNDRIES Demonstrate Custom 28nm SoC Using 2.5D Technology

Open-Silicon, Inc. and GLOBALFOUNDRIES announced the demonstration of a functional system-on-chip (SoC) solution featuring two 28nm logic chips, with embedded ARM processors, connected across a 2.5D silicon interposer. The jointly developed design is a proof-of-concept vehicle to showcase the benefits of 2.5D technology for mobile and low-power server applications. At the heart of the custom SoC are two ARM Cortex-A9 processors manufactured using GLOBALFOUNDRIES' 28nm-SLP (Super Low Power) process technology. The processors are attached to a silicon interposer, which is built on a 65nm manufacturing flow with through-silicon-vias (TSVs) to enable high-bandwidth communication between the chips. This approach allows designers to choose the most appropriate process technology for each function of their SoC, while the interposer and TSVs allow for finer grain and lower power connectivity than traditional packaging solutions, leading to smaller form factors and reduced power budgets for next-generation electronic devices. Open-Silicon and GLOBALFOUNDRIES developed the custom SoC to help overcome some of the challenges associated with bringing 2.5D technology to market. The 2.5D system features the following characteristics: logic die including dual-core ARM Cortex-A9 CPUs, as well as DDR3, USB and AXI bridge interfaces, special EDA reference flow designed to address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing, support for additional verification steps brought on by 2.5D design rules, custom die-to-die IO for better area and power characteristics providing a maximum of 8GB/s full-duplex data-rate across the two die through the silicon interposer, development board with memory, boot-ROM, and basic peripherals to demonstrate the die-to-die interface functionality through software running on the CPUs embedded in the logic dies, test methodology consisting of Boundary Scan and Loopback modes, package-related design rules, back-side integration, copper pillar micro-bumping, and 2.5D product assembly by Amkor Technology.

Open-Silicon, Inc. Presents at 15th Annual Needham Growth Conference, Jan-16-2013 01:50 PM

Open-Silicon, Inc. Presents at 15th Annual Needham Growth Conference, Jan-16-2013 01:50 PM. Venue: New York Palace Hotel, 455 Madison Avenue, New York, NY 10022, United States.

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