National Semiconductor Corporation introduced WEBENCH® Visualizer, a powerful comparison and selection tool that enables engineers to rapidly select an optimal power system design. WEBENCH Visualizer creates a graphical snapshot of options across multiple criteria, such as power efficiency, footprint and system bill of materials (BOM) cost. Drawing from 25 different switching power supply architectures and 21,000 components, engineers can navigate through billions of power supply design alternatives in seconds. Design criteria can be modified and the real-time effects observed, allowing engineers to select the best DC-DC power supply based on their unique needs. The WEBENCH Visualizer tool features an optimizer dial that enables engineers to 'dial-in' their preference for footprint, system BOM cost and power efficiency. The tool instantly creates 50-70 designs from 48 billion possible design options. It then highlights the smallest and most efficient designs, with one recommended as a starting point for further optimization. A second visualizer control panel allows engineers to adjust their design options for voltage, current and temperature. In seconds, an updated set of solutions appears, highlighting each design's topology, schematic, footprint, efficiency, operating values and BOM cost/count. The tool's interactive filter allows engineers to further fine-tune the power supply design to meet the target system's exact requirements. The WEBENCH Visualizer tool is an extension of National's WEBENCH tools for LEDs and power design. These tools offer instant access to the latest simulation models, parametric data and package information, enabling designers to simultaneously compare the performance of multiple devices in multiple circuit requirements.

National Semiconductor Corporation - Conference Presentation Calls

National Semiconductor Corporation announced the availability of an intermediate frequency (IF) sampling receiver reference design for multi-carrier, multi-standard wireless base stations addressing GSM/EDGE, WCDMA, LTE and WiMAX standards. The subsystem reference design kit gives radio designers the necessary technical material-reference design board, software, schematic, bill of materials and Gerber files-to accelerate the design and development of high-performance radio receivers. The SP16160CH1RB reference design board facilitates evaluation of the IF receive signal path performance under a variety of input conditions. When combined with a low-noise, high-linearity RF front-end and sufficient IF filtering, the reference design enables high sensitivity receivers that exceed the stringent multi-carrier GSM requirements in both normal and blocking conditions. Improved receiver sensitivity translates to enhanced base station capacity and coverage, allowing service providers to reach more customers and deliver a higher quality of service. The SP16160CH1RB delivers an IF chain receiver sensitivity of-105 dBm, with a 9 dB carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF. With the digitally-controlled variable gain amplifier (DVGA) set at a maximum gain of 22 dB, the sensitivity is limited primarily by the noise contribution of the DVGA. In the presence of a strong blocker, with the DVGA gain set at 12 dB and blocker level kept at 1.6 dBm input to the ADC, the SP16160CH1RB board delivers sensitivity of-86 dBm. In this blocking condition, the receiver sensitivity is determined by the ADC's high spurious-free dynamic range.