Last $18.99 USD
Change Today +0.285 / 1.52%
Volume 5.5M
CDNS On Other Exchanges
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As of 8:10 PM 12/19/14 All times are local (Market data is delayed by at least 15 minutes).

cadence design sys inc (CDNS) Snapshot

Open
$18.84
Previous Close
$18.70
Day High
$19.02
Day Low
$18.61
52 Week High
11/28/14 - $19.03
52 Week Low
12/23/13 - $13.46
Market Cap
5.6B
Average Volume 10 Days
2.5M
EPS TTM
$0.55
Shares Outstanding
292.7M
EX-Date
--
P/E TM
34.5x
Dividend
--
Dividend Yield
--
Current Stock Chart for CADENCE DESIGN SYS INC (CDNS)

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cadence design sys inc (CDNS) Details

Cadence Design Systems, Inc. develops, sells or leases, and licenses electronic design automation (EDA) software, emulation hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems companies worldwide. It offers functional verification products, including logic verification software that enable customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization; design IP products consisting of pre-verified, customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. The company also provides custom integrated circuits (ICs) design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs. In addition, the company provides digital IC design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products, which are used in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry. Further, it offers system interconnect design products to develop printed circuit boards and IC packages; and design for manufacturing products to address manufacturing and yield issues in the product development process. Additionally, the company offers engineering, methodology, education, and hosted design solutions. Cadence Design Systems, Inc. was founded in 1988 and is headquartered in San Jose, California.

5,700 Employees
Last Reported Date: 02/20/14
Founded in 1988

cadence design sys inc (CDNS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer, Principal Accounting...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $400.0K
Chief of Staff to The Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDNS) Key Developments

Fujitsu Kansai-Chubu Net-Tech Limited Utilizes the Cadence® C-to-Silicon Compiler

Cadence Design Systems Inc. announced that Fujitsu Kansai-Chubu Net-Tech Limited utilized the Cadence® C-to-Silicon Compiler to shorten turnaround time by 40% compared to its traditional RTL process for a complex 100G transport system design. KCN used the SystemC-based design approach for the transport system pipelines, reducing code size by more than half, and used the C-to-Silicon Compiler high-level synthesis for quick iterations to tune the functional specification and generate the optimized RTL implementation. By changing the design constraints to the C-to-Silicon Compiler, KCN was able to explore different micro-architectures and significantly reduced the place-and-route turnaround time. Fixing a place-and-route issue with traditional RTL design at Fujitsu took three days, but only half a day with the C-to-Silicon Compiler.

GLOBALFOUNDRIES and Cadence Deliver First Soc Enablement Solution Featuring ARM Cortex-A17 Processor

Cadence Design Systems Inc. announced the delivery of quad-core silicon built around the ARM® Cortex®-A17 processor implemented using GLOBALFOUNDRIES’ 28nm Super Low Power (28nm-SLP) process with High-k Metal Gate (HKMG) technology. GLOBALFOUNDRIES utilized Cadence® tools exclusively to achieve 2.0GHz processor performance at typical operating conditions, which matched pre-silicon design performance predicted by Cadence Tempus™ Timing Signoff Solution analysis. The Cadence tools used in this successful design include Encounter® Digital Implementation System, Encounter RTL Compiler, Quantus™ QRC Extraction Solution, Tempus Timing Signoff Solution, Encounter Conformal® Equivalence Checker, Physical Verification System and Litho Physical Analyzer. The flow incorporated physical IP technology from the ARM POP™ IP suite to leverage the full performance range of the 28nm-SLP process. Based on the success of this design, Cadence and GLOBALFOUNDRIES have also completed the tapeout of a second chip using the latest ARM Cortex-A17 processor RTL, achieving a 23% single-core area reduction versus the previous tapeout, while meeting the 2.0GHz maximum frequency signoff target. The second tapeout included the full suite of ARM POP IP, including the optimized memory instances for Cortex-A17. In addition, the Cadence Voltus™ IC Power Integrity solution was used throughout the design of the next-generation quad-core tapeout to guide and validate the power grid and enable the implementation of advanced power shutoff technologies. Encounter Conformal Low Power was used to verify the power-intent specification for the design. GLOBALFOUNDRIES’ 28nm-SLP technology is ideally suited for the next generation of mobile devices and low power Internet of Things (IoT) solutions, enabling designs with faster processing speeds, smaller feature sizes, lower standby power and longer battery life. The technology is based on GLOBALFOUNDRIES’ "Gate First" approach to HKMG, which has been in volume production for nearly four years. The technology offers a combination of performance, power efficiency and cost that is ideally suited for the mobile and IoT market.

HiSilicon Technologies Expands Adoption of Cadence Design Systems, Inc. Tools and IP for Advanced-Node FinFET Designs

Cadence Design Systems Inc. announced that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16 nanometer FinFET designs, and to collaborate on the design flow for 10 nanometer and 7 nanometer nodes. HiSilicon has also broadly adopted Cadence digital and custom/analog verification solutions, and has licensed Cadence DDR IP and the Cadence 3D-IC solution to deploy multiple heterogeneous dies in a single package on a silicon interposer substrate. For the digital flow, the agreement includes access to Cadence Encounter Digital Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, and Quantus QRC Extraction Solution. For custom/analog design, HiSilicon designers are using Cadence Virtuoso custom design platform, Spectre simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor. The agreement also includes an increase in licenses of Incisive Enterprise Simulator for advanced verification. For 3D-IC designs, HiSilicon is utilizing the Cadence 3D-IC solution, which includes Encounter Digital Implementation System and Allegro tools for IC/package co-design, and Voltus and Sigrity solutions for power, thermal and signal integrity verification.

 

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CDNS

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Valuation CDNS Industry Range
Price/Earnings 43.7x
Price/Sales 3.5x
Price/Book 4.3x
Price/Cash Flow 36.1x
TEV/Sales 3.0x
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