Last €12.53 EUR
Change Today -0.199 / -1.56%
Volume 0.0
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cadence design sys inc (CDS) Snapshot

Open
€12.59
Previous Close
€12.72
Day High
€12.69
Day Low
€12.53
52 Week High
07/7/14 - €12.88
52 Week Low
10/31/13 - €9.08
Market Cap
3.6B
Average Volume 10 Days
0.0
EPS TTM
--
Shares Outstanding
289.5M
EX-Date
--
P/E TM
--
Dividend
--
Dividend Yield
--
Current Stock Chart for CADENCE DESIGN SYS INC (CDS)

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cadence design sys inc (CDS) Details

Cadence Design Systems, Inc. develops, sells or leases, and licenses electronic design automation (EDA) software, emulation hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems companies worldwide. It offers functional verification products, including logic verification software that enable customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization; design IP products consisting of pre-verified, customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. The company also provides custom integrated circuits (ICs) design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs. In addition, the company provides digital IC design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products, which are used in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry. Further, it offers system interconnect design products to develop printed circuit boards and IC packages; and design for manufacturing products to address manufacturing and yield issues in the product development process. Additionally, the company offers engineering, methodology, education, and hosted design solutions. Cadence Design Systems, Inc. was founded in 1988 and is headquartered in San Jose, California.

5,700 Employees
Last Reported Date: 02/20/14
Founded in 1988

cadence design sys inc (CDS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer, Principal Accounting...
Total Annual Compensation: $400.0K
Senior Vice President of Worldwide Field Oper...
Total Annual Compensation: $400.0K
Chief of Staff to The Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDS) Key Developments

Hitachi Chooses Cadence Design Systems Tempus Timing Signoff Solution

Cadence Design Systems Inc. announced that Hitachi has taped out its latest giga-scale design using the Cadence Tempus(TM) Timing Signoff Solution. Hitachi also utilized Tempus Timing Signoff Optimization (TSO), resulting in a reduction of their overall closure time to just 3 weeks down from almost 2 months. This represents a significant improvement in ECO iterations versus their previous solution. The Tempus solution's advanced capabilities were able to analyze over 50M cells flat in the design, an analysis that normally requires a hierarchical signoff flow. Hierarchical strategies were used extensively during the implementation phase; however, flat analysis was needed at signoff to ensure the best accuracy. The Tempus solution is the lead tool in a new class of massively parallel timing signoff tools and capabilities, which enable customers to shrink timing signoff closure and analysis turnaround time to a minimum. In addition to faster time-to-tapeout, designs are produced with less pessimism, area and power consumption through physically aware and path-based analysis optimization. By combining the massively parallelized capabilities of Tempus and QRC together and leveraging native database formats, Hitachi was able to improve time-to-tapeout well beyond those of existing mixed tool flows.

MegaChips Adopts Cadence RTL-to-Signoff Solution

Cadence Design Systems Inc. announced that MegaChips has cut its tapeout schedule in half by using the Cadence(R) digital RTL-to-Signoff solution. In addition to getting their products to market faster, MegaChips leveraged Cadence Encounter(R) RTL Compiler and Cadence Encounter Digital Implementation (EDI) System, and achieved a 9% frequency increase and an 8% power reduction on their dual-core ARM(R) Cortex(R)-A9 design. MegaChips also utilized the Cadence digital RTL-to-Signoff solution to address implementation challenges in hierarchical design/partitioning, congestion handling and better clock tree synthesis (CTS) structures. Encounter RTL Compiler's unique physically aware datapath optimization technology was able to reduce the area of critical blocks in the MegaChips design, while enabling faster timing closure through access of physical data earlier on in the design flow. The EDI System's multi-threaded GigaOpt physical optimization and CCOpt concurrent clock-data-path optimization with useful skew resulted in faster turnaround time with improved performance, and leakage and dynamic power.

NextG-Com Announces Availability of LTE Protocol Stack on Cadence Design Systems, Inc.'s Tensilica Processor

Cadence Design Systems Inc. and NextG-Com announced that NextG-Com has completed its port of the ALPS520 LTE Layer 2 and 3 protocol to the Cadence(R) Tensilica(R) ConnX BSP3 processor core. This combined hardware/software solution can be used to speed the design of LTE modems for cellular phones, tablets and other end-user equipment. The NextG-Com ALPS520 LTE protocol stack implements Layers 2 and 3 for FDD and TDD User Equipment (UE) terminals compliant to 3GPP Release 11. The ALPS520 is fully tested against 3GPP 36.523 conformance tests. The protocol stack components also come with a host of tools (Trace, ASN.1, SE-RTOS(TM)), which aid in faster product development. The ConnX BSP3 core is an optimized LTE Layer 1, 2 and 3 dataplane processor (DPU), ideal for system control and layers 2 and 3 protocol stacks. This core, coupled with the ConnX BBE DSP cores and the ConnX SSP16DPU, enables SoC developers to quickly implement software-programmable wireless communication modems.

 

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CDS

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Valuation CDS Industry Range
Price/Earnings 43.1x
Price/Sales 3.3x
Price/Book 4.1x
Price/Cash Flow 35.7x
TEV/Sales 2.7x
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