Last €13.12 EUR
Change Today +0.211 / 1.64%
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cadence design sys inc (CDS) Snapshot

Open
€13.09
Previous Close
€12.90
Day High
€13.12
Day Low
€13.01
52 Week High
10/6/14 - €13.95
52 Week Low
10/31/13 - €9.08
Market Cap
3.8B
Average Volume 10 Days
4.5
EPS TTM
--
Shares Outstanding
292.7M
EX-Date
--
P/E TM
--
Dividend
--
Dividend Yield
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Current Stock Chart for CADENCE DESIGN SYS INC (CDS)

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cadence design sys inc (CDS) Details

Cadence Design Systems, Inc. develops, sells or leases, and licenses electronic design automation (EDA) software, emulation hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems companies worldwide. It offers functional verification products, including logic verification software that enable customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization; design IP products consisting of pre-verified, customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. The company also provides custom integrated circuits (ICs) design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs. In addition, the company provides digital IC design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products, which are used in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry. Further, it offers system interconnect design products to develop printed circuit boards and IC packages; and design for manufacturing products to address manufacturing and yield issues in the product development process. Additionally, the company offers engineering, methodology, education, and hosted design solutions. Cadence Design Systems, Inc. was founded in 1988 and is headquartered in San Jose, California.

5,700 Employees
Last Reported Date: 02/20/14
Founded in 1988

cadence design sys inc (CDS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer, Principal Accounting...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $400.0K
Chief of Staff to The Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDS) Key Developments

Cadence Design Systems Inc. Announces Broad Portfolio of 3D Memory Verification IP

Cadence Design Systems Inc. announced the immediate availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications. Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager. Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.

Cadence Design Systems Inc. Announces Availability of Optimized Port of Müller-BBM's m|klang ANC and ASD Software

Cadence Design Systems Inc. announced that an optimized port of Müller-BBM's m|klang ANC and ASD software is now available on the Cadence Tensilica HiFi Audio/Voice digital signal processing (DSP) family. This is the first time m|klang ANC and ASD software has been ported to a licensable intellectual property (IP) DSP core. m|klang ANC and ASD are successfully used by leading global OEMs to reduce in-vehicle noise, and to create unique vehicle sound and driving experiences of their production vehicles. Having the technology available on HiFi processors now allows integrating these premium audio system features into mainstream automotive head units, making them available to a broad range of cars and customers. The first vehicles to utilize m|klang on HiFi processors are expected at dealerships later this year.

Cadence Design Systems Inc. Introduces Automotive Functional Safety Verification Solution

Cadence Design Systems Inc. introduced its new automotive functional safety verification solution, which reduces the effort required by automotive designers to prepare for ISO 26262 compliance by up to 50%. An expansion to the Cadence Incisive functional verification platform, the new fault injection and safety verification technologies help automotive engineers automate ISO 26262 compliance for traceability, safety verification and tool confidence level (TCL). The integrated Cadence Incisive functional safety solution reduces the compliance effort by automating the time-intensive manual verification process of fault injection and result analysis for IP, System-on-Chip (SoC) and system designs. The solution includes the Incisive Functional Safety Simulator and the Functional Safety Analysis capability in the Incisive vManager(TM) solution. The new simulator operates within the Incisive Enterprise Simulator compiled-code engine, boosting runtime performance up to 10x and providing the seamless reuse of the functional and mixed-signal verification environments to accelerate the time to develop safety verification versus the interpreted Incisive Verifault-XL engine traditionally used in functional safety simulation. The ability of safety systems to detect faults is the critical measurement for ISO 26262 compliance. The Functional Safety Analysis capability allows the safety engineer to automatically generate a safety verification regression from the fault dictionary created by the simulator and enables the Incisive vManager solution to track millions of detected, partially detected, and undetected faults introduced into simulation to verify the safety systems in a design. By automating the tracking of these safety metrics, the Incisive functional safety solution automates man-years of effort, and provides the traceable audit trail needed in the systems design chain from semiconductor to OEM suppliers.

 

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Price/Sales 3.1x
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Price/Cash Flow 31.1x
TEV/Sales 2.5x
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