Last €13.54 EUR
Change Today +0.076 / 0.56%
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cadence design sys inc (CDS) Snapshot

Open
€13.60
Previous Close
€13.46
Day High
€13.70
Day Low
€13.54
52 Week High
09/8/14 - €13.89
52 Week Low
10/31/13 - €9.08
Market Cap
3.9B
Average Volume 10 Days
0.0
EPS TTM
--
Shares Outstanding
290.0M
EX-Date
--
P/E TM
--
Dividend
--
Dividend Yield
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Current Stock Chart for CADENCE DESIGN SYS INC (CDS)

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cadence design sys inc (CDS) Details

Cadence Design Systems, Inc. develops, sells or leases, and licenses electronic design automation (EDA) software, emulation hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems companies worldwide. It offers functional verification products, including logic verification software that enable customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization; design IP products consisting of pre-verified, customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. The company also provides custom integrated circuits (ICs) design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs. In addition, the company provides digital IC design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products, which are used in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry. Further, it offers system interconnect design products to develop printed circuit boards and IC packages; and design for manufacturing products to address manufacturing and yield issues in the product development process. Additionally, the company offers engineering, methodology, education, and hosted design solutions. Cadence Design Systems, Inc. was founded in 1988 and is headquartered in San Jose, California.

5,700 Employees
Last Reported Date: 02/20/14
Founded in 1988

cadence design sys inc (CDS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer, Principal Accounting...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $400.0K
Chief of Staff to The Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDS) Key Developments

TSMC Adopts Cadence Design Systems Inc. Solutions for 16nm FinFET Library Characterization

Cadence Design Systems Inc. announced that TSMC has adopted Cadence(R) solutions for 16nm FinFET library characterization. Developed in collaboration between Cadence and TSMC, the library characterization tool setting is available to TSMC customers for download on TSMC-Online. The setting is based on Cadence Virtuoso(R) Liberate(R) Characterization Solution and Spectre(R) Circuit Simulator, and includes environment setup and sample templates for TSMC standard cells. Utilizing native Spectre API integration, the combination of the Liberate solution and Spectre Circuit Simulator delivers superior convergence and accuracy, enabling mutual customers to speed up their library characterization cycle. In testing performed with TSMC, the combined Cadence characterization and simulation solution reduced the turnaround time by half for 16nm FinFET standard and complex cell-characterization cycles. As a result, TSMC has incorporated the Liberate solution with Spectre Circuit Simulator into its library characterization production flow for the latest 16nm FinFET libraries. Libraries characterized by the Cadence characterization solution were used in the 16nm FinFET v1.0 static timing analysis (STA) tool certification, including the Cadence Tempus(TM) Timing Signoff Solution and other STA tools. The reference kit gives TSMC customers the tools needed to enable re-characterization that addresses their specific design challenges with a consistent methodology that meets TSMC's stringent accuracy and performance requirements. The Liberate solution also continues to support third-party circuit simulators.

Cadence Design Systems Inc. Introduces Voltus-Fi Custom Power Integrity Solution

Cadence Design Systems Inc. introduced Cadence Voltus-Fi Custom Power Integrity Solution, a transistor-level electromigration and IR-drop solution that delivers foundry-certified SPICE-level accuracy in power signoff to create the fastest path to design closure. The new solution is enabled by Cadence Spectre Accelerated Parallel Simulator signoff SPICE simulation, providing best-in-class accuracy at the transistor level to meet complex manufacturing specifications at advanced nodes. It complements Cadence Voltus IC Power Integrity Solution, a full-chip, cell-level power signoff tool, and completes the company's power signoff technology solution. Voltus-Fi Custom Power Integrity Solution enables designers to shrink the critical power signoff closure and analysis phase through key capabilities including: Cadence's patented voltage-based iteration method, which requires a smaller memory footprint and runs faster than the traditional current-based iteration method. Full integration with the Cadence Virtuoso platform, which provides a single design flow that improves designer productivity in analog and custom block EMIR signoff. Leverages transistor-level parasitic extraction with Cadence Quantus QRC Extraction Solution, transistor-level simulation with Cadence Spectre Accelerated Parallel Simulator and Cadence Spectre Extensive Partitioning Simulator and, finally, EMIR results visualization on real physical layouts for quick analysis, debugging and optimization. Integration between Voltus-Fi Custom Power Integrity Solution and Voltus IC Power Integrity Solution, which provides a seamless flow for advanced analog/mixed-signal power signoff for designs with mixed transistor-level and cell-level blocks.

Cadence Design Systems, Inc. Announces Protium Rapid Prototyping Platform and Expands System Development Suite Low-Power Verification

Cadence Design Systems Inc. announced an expansion of its System Development Suite with the addition of the new Cadence® Protium(TM) rapid prototyping platform for improved software development productivity, and IEEE 1801 low power standard support in Cadence Palladium® XP II verification computing platform. These expansions to the Cadence System Development Suite enable system and semiconductor companies in the mobile, consumer, networking and storage segments to efficiently address important design challenges such as early software bring-up and reduced power consumption. Built using Xilinx® Virtex®-7 2000T FPGAs, the Protium platform is Cadence's second-generation FPGA prototyping platform for software development. It improves productivity by reducing prototype bring-up time by up to 70% versus competitive solutions, shortening the process from months to weeks. Featuring Palladium flow compatibility, a 4X increase in capacity versus the previous generation, and support for up to 100 million gates, the Protium platform enables software development and throughput regressions supported by a fully automatic flow and the capability to execute user-driven performance optimizations. The Protium platform also provides automated memory compilation, external bulk memory support, and RTL name preservation throughout the flow, which minimizes the tedious and error-prone manual FPGA bring-up steps, thereby speeding up time to market. Low-power analysis and verification is a key part of system and system-on-chip (SoC) signoff criteria. Addressing this, Cadence has expanded the Dynamic Power Analysis in the Palladium XP II platform beyond Common Power Format (CPF) support, adding verification and debug support for the IEEE 1801 standard. The Cadence System Development Suite now offers an integrated and consistent low-power flow for engineers using either of the power standards across the Incisive® formal and simulation and Palladium platforms, with common power plan and metrics, and integrated debug analysis.

 

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Valuation CDS Industry Range
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Price/Sales 3.3x
Price/Book 4.1x
Price/Cash Flow 33.4x
TEV/Sales 2.7x
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