Last €14.85 EUR
Change Today +0.103 / 0.70%
Volume 0.0
CDS On Other Exchanges
Symbol
Exchange
NASDAQ GS
Frankfurt
As of 12:09 PM 11/24/14 All times are local (Market data is delayed by at least 15 minutes).

cadence design sys inc (CDS) Snapshot

Open
€14.80
Previous Close
€14.75
Day High
€14.85
Day Low
€14.71
52 Week High
11/10/14 - €15.02
52 Week Low
11/26/13 - €9.39
Market Cap
4.3B
Average Volume 10 Days
10.0
EPS TTM
--
Shares Outstanding
292.7M
EX-Date
--
P/E TM
--
Dividend
--
Dividend Yield
--
Current Stock Chart for CADENCE DESIGN SYS INC (CDS)

cadence design sys inc (CDS) Related Businessweek News

No Related Businessweek News Found

cadence design sys inc (CDS) Details

Cadence Design Systems, Inc. develops, sells or leases, and licenses electronic design automation (EDA) software, emulation hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems companies worldwide. It offers functional verification products, including logic verification software that enable customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization; design IP products consisting of pre-verified, customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. The company also provides custom integrated circuits (ICs) design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs. In addition, the company provides digital IC design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products, which are used in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry. Further, it offers system interconnect design products to develop printed circuit boards and IC packages; and design for manufacturing products to address manufacturing and yield issues in the product development process. Additionally, the company offers engineering, methodology, education, and hosted design solutions. Cadence Design Systems, Inc. was founded in 1988 and is headquartered in San Jose, California.

5,700 Employees
Last Reported Date: 02/20/14
Founded in 1988

cadence design sys inc (CDS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer, Principal Accounting...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $400.0K
Chief of Staff to The Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDS) Key Developments

Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development

Cadence Design Systems Inc. announced that Sonics Inc. has adopted Cadence(R) JasperGold(R) Apps in the formal verification methodology for its intellectual property (IP). Sonics' on-chip network IP integrates multiple heterogeneous cores in a system-on-chip (SoC) using configurable interconnect fabric and multiple, on-chip communication protocols including the native PIF interface of Cadence(R) Tensilica(R) Xtensa(R) DPUs. Sonics is initially deploying the JasperGold Apps to speed the extensive validation of its protocol conversion logic. Part of the Cadence System Development Suite, JasperGold Apps perform multiple formal-based verification tasks and leverage a common formal verification platform, database and user interface. JasperGold Apps automate property creation for many common verification tasks, enabling rapid adoption by both design and verification engineers without previous formal experience. All JasperGold Apps leverage the Cadence Jasper Visualize(TM) graphical visualization and debug technology for fast debugging and a consistent user experience. Verification of configurable interfaces is a challenging task, as traditional simulation environments aren't well suited to handle their complexity. Exhaustive verification of highly configurable on-chip networks that integrate multicore SoCs requires both stimulus-driven simulation and formal proof technologies. To ensure the quality IP, the network transactions must be checked across communication protocol boundaries. Simulation alone is insufficient to fully check the transfer function of the network. JasperGold readily accepts commonly available formats like SystemVerilog Assertions (SVA) as its input and has easily scripted setup controls, enabling easy integration with other verification environments. By allowing Sonics to use exactly the same SVA protocol checkers for both simulation and formal verification, the use of JasperGold Apps can help eliminate an entire class of bring-up and ongoing issues.

Cadence Design Systems Inc. Announces First 25G Ethernet Verification IP

Cadence Design Systems Inc. announced the Verification IP (VIP) supporting the new 25-Gigabit (25G) Ethernet specification. The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence(R) 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected. This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25% bandwidth improvement compared to 40G.

Cadence Design Systems Inc. Announces Virtuoso Liberate AMS Characterization Solution

Cadence Design Systems Inc. announced the Cadence(R) Virtuoso(R) Liberate(TM) AMS characterization solution, first dynamic simulation characterization solution for mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os. Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff. With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty(TM) representations are required for all blocks in the design including mixed-signal macros. To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library. To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre(R) XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks. This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models. For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.

 

Stock Quotes

Market data is delayed at least 15 minutes.

Company Lookup
Recently Viewed
CDS:GR €14.85 EUR +0.103

CDS Competitors

Market data is delayed at least 15 minutes.

Company Last Change
Informatica Corp $36.55 USD +0.25
Open Text Corp C$64.70 CAD +0.12
PTC Inc $38.31 USD -0.045
Synopsys Inc $42.75 USD +0.26
TIBCO Software Inc $23.81 USD +0.051
View Industry Companies
 

Industry Analysis

CDS

Industry Average

Valuation CDS Industry Range
Price/Earnings 42.4x
Price/Sales 3.4x
Price/Book 4.2x
Price/Cash Flow 35.1x
TEV/Sales 2.9x
 | 

Sponsored Financial Commentaries

Sponsored Links

Report Data Issue

To contact CADENCE DESIGN SYS INC, please visit www.cadence.com. Company data is provided by Capital IQ. Please use this form to report any data issues.

Please enter your information in the following field(s):
Update Needed*

All data changes require verification from public sources. Please include the correct value or values and a source where we can verify.

Your requested update has been submitted

Our data partners will research the update request and update the information on this page if necessary. Research and follow-up could take several weeks. If you have questions, you can contact them at bwwebmaster@businessweek.com.