Last €15.50 EUR
Change Today +0.174 / 1.14%
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cadence design sys inc (CDS) Snapshot

Open
€15.48
Previous Close
€15.32
Day High
€15.56
Day Low
€15.33
52 Week High
12/23/14 - €15.56
52 Week Low
12/27/13 - €9.90
Market Cap
4.5B
Average Volume 10 Days
5.0
EPS TTM
--
Shares Outstanding
292.7M
EX-Date
--
P/E TM
--
Dividend
--
Dividend Yield
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Current Stock Chart for CADENCE DESIGN SYS INC (CDS)

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cadence design sys inc (CDS) Details

Cadence Design Systems, Inc. develops, sells or leases, and licenses electronic design automation (EDA) software, emulation hardware, verification intellectual property (VIP), and design intellectual property (design IP) for semiconductor and electronics systems companies worldwide. It offers functional verification products, including logic verification software that enable customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure; system design and verification products for hardware-software verification, as well as for system power exploration, analysis, and optimization; design IP products consisting of pre-verified, customizable functional blocks to integrate into customer’s SoCs; and VIP and memory models for use in system-level verification to model correct behavior of full systems interacting with their environments. The company also provides custom integrated circuits (ICs) design and verification products to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory, and RF designs. In addition, the company provides digital IC design products, such as logic design products for chip planning, design, verification, and test technologies and services; physical implementation products, which are used in place and route, signal integrity, optimization, and double patterning preparation; and signoff products to signoff the design as ready for manufacture by a silicon foundry. Further, it offers system interconnect design products to develop printed circuit boards and IC packages; and design for manufacturing products to address manufacturing and yield issues in the product development process. Additionally, the company offers engineering, methodology, education, and hosted design solutions. Cadence Design Systems, Inc. was founded in 1988 and is headquartered in San Jose, California.

5,700 Employees
Last Reported Date: 02/20/14
Founded in 1988

cadence design sys inc (CDS) Top Compensated Officers

Chief Executive Officer, President, Director ...
Total Annual Compensation: $650.0K
Chief Financial Officer, Principal Accounting...
Total Annual Compensation: $400.0K
Executive Vice President of Worldwide Field O...
Total Annual Compensation: $400.0K
Chief of Staff to The Chief Executive Officer...
Total Annual Compensation: $375.0K
Senior Vice President of Research & Developme...
Total Annual Compensation: $350.0K
Compensation as of Fiscal Year 2013.

cadence design sys inc (CDS) Key Developments

HiSilicon Technologies Expands Adoption of Cadence Design Systems, Inc. Tools and IP for Advanced-Node FinFET Designs

Cadence Design Systems Inc. announced that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16 nanometer FinFET designs, and to collaborate on the design flow for 10 nanometer and 7 nanometer nodes. HiSilicon has also broadly adopted Cadence digital and custom/analog verification solutions, and has licensed Cadence DDR IP and the Cadence 3D-IC solution to deploy multiple heterogeneous dies in a single package on a silicon interposer substrate. For the digital flow, the agreement includes access to Cadence Encounter Digital Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, and Quantus QRC Extraction Solution. For custom/analog design, HiSilicon designers are using Cadence Virtuoso custom design platform, Spectre simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor. The agreement also includes an increase in licenses of Incisive Enterprise Simulator for advanced verification. For 3D-IC designs, HiSilicon is utilizing the Cadence 3D-IC solution, which includes Encounter Digital Implementation System and Allegro tools for IC/package co-design, and Voltus and Sigrity solutions for power, thermal and signal integrity verification.

Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development

Cadence Design Systems Inc. announced that Sonics Inc. has adopted Cadence(R) JasperGold(R) Apps in the formal verification methodology for its intellectual property (IP). Sonics' on-chip network IP integrates multiple heterogeneous cores in a system-on-chip (SoC) using configurable interconnect fabric and multiple, on-chip communication protocols including the native PIF interface of Cadence(R) Tensilica(R) Xtensa(R) DPUs. Sonics is initially deploying the JasperGold Apps to speed the extensive validation of its protocol conversion logic. Part of the Cadence System Development Suite, JasperGold Apps perform multiple formal-based verification tasks and leverage a common formal verification platform, database and user interface. JasperGold Apps automate property creation for many common verification tasks, enabling rapid adoption by both design and verification engineers without previous formal experience. All JasperGold Apps leverage the Cadence Jasper Visualize(TM) graphical visualization and debug technology for fast debugging and a consistent user experience. Verification of configurable interfaces is a challenging task, as traditional simulation environments aren't well suited to handle their complexity. Exhaustive verification of highly configurable on-chip networks that integrate multicore SoCs requires both stimulus-driven simulation and formal proof technologies. To ensure the quality IP, the network transactions must be checked across communication protocol boundaries. Simulation alone is insufficient to fully check the transfer function of the network. JasperGold readily accepts commonly available formats like SystemVerilog Assertions (SVA) as its input and has easily scripted setup controls, enabling easy integration with other verification environments. By allowing Sonics to use exactly the same SVA protocol checkers for both simulation and formal verification, the use of JasperGold Apps can help eliminate an entire class of bring-up and ongoing issues.

Cadence Design Systems Inc. Announces First 25G Ethernet Verification IP

Cadence Design Systems Inc. announced the Verification IP (VIP) supporting the new 25-Gigabit (25G) Ethernet specification. The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence(R) 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected. This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25% bandwidth improvement compared to 40G.

 

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Valuation CDS Industry Range
Price/Earnings 44.3x
Price/Sales 3.6x
Price/Book 4.4x
Price/Cash Flow 36.6x
TEV/Sales 3.1x
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