Mentor Graphics Corp. and Tezzaron Semiconductor Corp. announced that they are collaborating to integrate the Mentor(R) Calibre(R) 3DSTACK product into Tezzaron's 3D-IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market. Tezzaron works with industry, academia, and government to create advanced 3D-ICs. Their offerings include wafer stacking and die stacking technology with TSVs, Bi-STAR(R) built in self-test and repair circuitry for continuous error detection and recovery, and extremely fast memory devices for both standalone and stacked applications. Complementing Tezzaron's 3D-IC design capabilities, the Calibre 3DSTACK signoff solution provides DRC, LVS, and parasitic extraction (PEX) capabilities. It verifies physical offset, rotation, and scaling at the die interfaces. It also enables connectivity tracing and extraction of interface parasitic elements needed for multi-die performance simulation. The Calibre 3DSTACK product is a fully compatible extension to the standard Calibre signoff platform, so it can be easily added to existing verification flows to support flexible stacking configurations of multiple dies, including dies based on different technologies or process nodes.

Mentor Graphics Corp. announced that MagnaChip Semiconductor Corporation has adopted the Pyxis(R) custom IC design platform and the Mentor(R) process design kit (PDK) automation process. MagnaChip added the Mentor Graphics(R) analog mixed-signal (AMS) design and verification solution that could handle a high level of mixed-signal complexity, different levels of design abstraction, and support multiple CAD tools in an integrated, unified environment. A key desired attribute was a reliable process for automating the creation of PDKs that could be easily inserted into their AMS design and verification flow.

Mentor Graphics Corp. announced availability of the newest tool in the Capital(R) software suite, Capital Harness(TM) TVM. This tool automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company's cost models. Capital Harness TVM is part of the Capital tool suite. The new tool adds rapid, accurate harness manufacturing process modeling and cost calculation capabilities to the Capital Define-Design-Build-Service flow. Capital Harness TVM addresses a critical business dynamic for wire harness suppliers: how to respond rapidly to requests for quotation. Rapid responses are needed both to win new business and to accommodate design changes, and are particularly challenging because wire harness manufacturing is typically a low-margin business. Capital Harness TVM provides rapid, highly detailed manufacturing cost data and also supports process choice and sourcing decisions, thus delivering total value management. Capital Harness TVM is a native Capital application, able to act directly on design data generated by other Capital tools. But it can also read data in several standard formats, including the emerging KBL standard. Capital Harness TVM can be implemented either as part of an extended Capital flow or stand-alone; data can also be received from the Mentor(R) mid-market VeSys(R) product, or from other industry tools.