Synopsys Inc. Delivered VDK for Renesas RH850 MCUs. Joint Center of Excellence Produces Virtualizer Development Kit Enabling Early Software Development, System Integration and Test for RH850-based Automotive Designs. New VDK for Renesas' RH850 MCU accelerates software development, system integration and test for a broad range of automotive applications, Seamless integration with tools such as Mathworks' Simulink(R) product, Synopsys' Saber and Vector's CANoe enables virtual Hardware-in-the-Loop (HIL) and fault testing, VDK can be customized to represent any RH850 MCU including the F1x, E1x, C1x and P1x series with the Synopsys Virtualizer(TM) tool set. The VDK for RH850 MCU includes reference virtual prototypes representing a microcontroller, including single and multicore versions of the RH850, timers, memories, communication blocks such as LIN, CAN and Ethernet and analog and error control modules. The initial release of the new VDK includes a virtual prototype following the F1x MCU memory map. The virtual prototype can be modified to represent other RH850 MCU series and to create additional VDKs, such as E1x, C1x and P1x, with the Virtualizer tool set. The VDK for RH850 MCU readily integrates with tools such as Mathworks Simulink.

Synopsys Inc. announced unaudited consolidated earnings results for the second quarter and six months ended April 30, 2013. For the quarter, the company reported total revenue of $499,257,000 against $432,561,000 a year ago. Operating income was $79,503,000 against $17,136,000 a year ago. Income before income taxes was $86,707,000 against $23,489,000 a year ago. Net income was $68,691,000 against $20,971,000 a year ago. Diluted net income per share was $0.44 against $0.14 a year ago. Non-GAAP net income was $103,664,000 against $78,498,000 a year ago. Non-GAAP net income per share was $0.66 against $0.53 a year ago. The company generated $134 million in cash from operations for the quarter. For the six months, the company reported total revenue of $974,394,000 against $858,057,000 a year ago. Operating income was $140,484,000 against $87,139,000 a year ago. Income before income taxes was $158,437,000 against $97,318,000 a year ago. Net income was $138,613,000 against $77,665,000 a year ago. Diluted net income per share was $0.89 against $0.52 a year ago. Non-GAAP net income was $206,631,000 against $160,828,000 a year ago. Non-GAAP net income per share was $1.33 against $1.08 a year ago. Net cash provided by operating activities was $42,292,000 against $87,456,000 a year ago. Purchases of property and equipment were $29,426,000 against $19,585,000 a year ago. For the third quarter of 2013, the company expects revenue to be in the range of $475 million to $485 million, tax rate applied in non-GAAP net income calculations to be in the range of 24% to 25%, GAAP earnings per share to be in the range of $0.28 to $0.34, non-GAAP earnings per share to be in the range of $0.53 to $0.55, and revenue from backlog approximately 90%. For the full year of 2013, the company expects revenue to be in the range of $1.955 billion to $1.975 billion, tax rate applied in non-GAAP net income calculations to be in the range of 23%, GAAP earnings per share to be in the range of $1.48 to $1.56, non-GAAP earnings per share to be in the range of $2.37 to $2.42, capital expenditures of approximately $70 million and cash flow from operations to be in the range of $375 million to $400 million.

Synopsys Inc. announced that Achronix Semiconductor has successfully used both Synopsys' IC Compiler(TM) physical design and IC Validator physical verification solutions to sign off its Speedster22i(R) FPGA -- the industry's first system-on-chip (SoC) design using FinFET transistors. Enabled by FinFET technology, Achronix's Speedster22i promises significant power, performance and cost benefits relative to competitive offerings. Synopsys' IC Compiler physical implementation tool has been enhanced to support correct-by-construction implementation of all FinFET-specific design rules, while the IC Validator physical verification tool used foundry rule decks to enable fast, accurate verification of FinFET-based SoCs and extraction of new FinFET device parameters. IC Compiler and IC Validator are now the standard solutions for place-and-route, design-rule-checking (DRC), and layout-vs.-schematic (LVS) checking in Achronix's design flow. Conventional approaches to continually shrink the conductive channel length of flat or planar transistors are facing serious limitations. In order to achieve acceptable switching performance, shorter conductive channel lengths tend to place additional burden on power and voltage. FinFET technology features non-planar (3D) transistor channels that wrap around a raised silicon "fin." FinFETs can be driven by a lower supply voltage and can switch transistors off completely, thereby reducing leakage and dynamic power consumption. Additionally, FinFETs can be switched on and off more rapidly, which increases maximum IC performance.