Last $20.10 USD
Change Today -0.08 / -0.40%
Volume 16.1M
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As of 8:04 PM 10/1/14 All times are local (Market data is delayed by at least 15 minutes).

taiwan semiconductor-sp adr (TSM) Snapshot

Open
$20.18
Previous Close
$20.18
Day High
$20.23
Day Low
$19.99
52 Week High
07/11/14 - $23.07
52 Week Low
02/5/14 - $16.44
Market Cap
104.2B
Average Volume 10 Days
11.7M
EPS TTM
--
Shares Outstanding
5.2B
EX-Date
07/14/14
P/E TM
--
Dividend
$0.50
Dividend Yield
2.48%
Current Stock Chart for TAIWAN SEMICONDUCTOR-SP ADR (TSM)

taiwan semiconductor-sp adr (TSM) Details

Taiwan Semiconductor Manufacturing Company Limited is engaged in manufacturing, selling, packaging, testing, and computer-aided designing integrated circuits and other semiconductor devices. It also manufactures masks. The company is involved in researching, developing, designing, manufacturing, and selling solid state lighting devices and related applications products and systems, as well as renewable energy and saving related technologies and products. In addition, it provides customer and technical support services; and sells and markets solar related products. The company operates in Taiwan, the United States, Asia, Europe, and internationally. Taiwan Semiconductor Manufacturing Company Limited was founded in 1987 and is headquartered in Hsinchu, Taiwan.

Founded in 1987

taiwan semiconductor-sp adr (TSM) Top Compensated Officers

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Executives, Board Directors

taiwan semiconductor-sp adr (TSM) Key Developments

Synopsys, Inc. Collaborates with TSMC to Develop an Expanded 16FF+ Custom Design

Synopsys Inc. announced that it has collaborated with TSMC to develop an expanded 16FF+ custom design reference flow using Synopsys' custom design solution. Part of TSMC's design infrastructure, the expanded custom reference flow adds new technologies to the schematic and layout environment to streamline and accelerate custom design for TSMC's 16FF+ process. Highlights of these improvements include new methods for design constraints management, estimation of layout-dependent effects prior to final layout, schematic-driven layout with FinFET devices, a simplified method to run pre- and post-layout simulation, and a streamlined graphical user interface for layout of matched devices and guard rings. In 16FF+ design, circuit designers need a smooth path for communicating constraints to the layout designer, and Synopsys provides a comprehensive solution for constraint management. Design constraints such as device matching, color assignment, symmetry and clustering can be added to schematics and passed to the layout editor to be enforced during layout. Additionally, the schematic environment has been updated with a simplified method for running pre- and post-layout circuit simulation and comparing the results. Speeding the analysis of layout parasitics reduces the time it takes to finalize the layout. The schematic environment has also been enhanced to support a schematic-driven layout flow for FinFET devices. In analog circuits, good device matching is needed to deliver performance margin and production yield. The matching device creator in Laker makes it easier to achieve quality custom layout with updated support for matched placement of FinFET devices. Now, density-aware device array placement, guard ring creation and dummy insertion are all handled through a simple graphical user interface (GUI). For analyzing layout-dependent effects, the custom design reference flow with Laker and TSMC's LDE-API provides a smooth path for back-annotating extracted device parameters to simulation after placement is completed.

TSMC and ARM Announce Results from Key FinFET Silicon Validation of ARM big.LITTLE Implementation, Using ARM Cortex(R)-A57 and Cortex-A53 Processors on TSMC's 16nm FinFET Process Technology

TSMC and ARM(R) announced the results from a key FinFET silicon validation of the ARM big.LITTLE(TM) implementation, using ARM Cortex(R)-A57 and Cortex-A53 processors on TSMC's advanced 16nm FinFET (16FF) process technology. Silicon results on 16FF show the big Cortex-A57 processor achieving 2.3GHz for sustained mobile peak performance, as well as the LITTLE Cortex-A53 processor consuming only 75mW for most common workloads. The performance improvements are a result of the collaboration between ARM and TSMC to jointly optimize the 64-bit ARMv8-A processor series on FinFET process technologies and build on the successful tape-out of the Cortex-A57 processor on TSMC's 16FF process last year. Ongoing collaborative efforts are focused on TSMC's 16FF+ process technology which will deliver an additional 11% gain in performance for the Cortex-A57 at the same power as the 16FF process, along with a further 35% power reduction for the Cortex-A53 when running low-intensity applications. This further increases the dynamic performance range and power savings for big.LITTLE platforms. 16FF+ is scheduled to be delivered by Fourth Quarter 2014. Early big.LITTLE implementations of Cortex-A57 and Cortex-A53 processors on 16FF+ are supported by ARM POP(TM) IP technology.

TSMC Launches Ultra-Low Power Technology Platform for IoT and Wearable Device Applications

TSMC announced the foundry segment's first and most comprehensive ultra-low power technology platform aimed at a wide range of applications for the rapidly evolving Internet of Things (IoT) and wearable device markets that require a wide spectrum of technologies to best serve these diverse applications. In this platform, TSMC offers multiple processes to provide significant power reduction benefits for IoT and wearable products and a comprehensive design ecosystem to accelerate time-to-market for customers. TSMC's ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products. Compared with their previous low power generations, TSMC's ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life -- by 2X to 10X - when much smaller batteries are demanded in IoT/wearable applications. One valuable advantage offered by TSMC's ultra-low power technology platform is that customers can leverage TSMC's existing IP ecosystem through the Open Innovation Platform(R). Designers can easily re-use IPs and libraries built on TSMC's low-power processes for new ultra-low power designs to boost first-silicon success rates and to achieve fast time-to-market product introduction. Some early design engagements with customers using 55ULP, 40ULP and 28ULP nodes are scheduled in 2014 and risk productions are planned in 2015.

 

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Industry Analysis

TSM

Industry Average

Valuation TSM Industry Range
Price/Earnings 15.5x
Price/Sales 4.8x
Price/Book 3.5x
Price/Cash Flow 15.5x
TEV/Sales 4.0x
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